The subject matter of the present application relates to packaged microelectronic elements and methods for packaging microelectronic elements, e.g., semiconductor elements.
Microelectronic elements, e.g., semiconductor chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself. Semiconductor chips are typically packaged together with other elements, e.g., chip carriers, lead frames or dielectric elements to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the packaged chip may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer or a cell phone.
Dielectric materials used for packaging semiconductor chips are selected for their compatibility with the processes used to form the packaged chips. For example, during solder or other bonding operations, intense heat may be applied. Accordingly, metal lead frames have been used as packaging elements. Laminates have also been used to package microelectronic devices. Laminate elements may include two to four alternating layers of fiberglass and epoxy, wherein successive fiberglass layers may be laid in traversing, e.g., orthogonal, directions. Optionally, heat resistive compounds such as bismaleimide triazine (BT) may be added to such laminate elements.
Tape-like dielectric elements have also been used to form thin profile microelectronic packages. Such tapes are typically provided in the form of sheets or rolls of sheets. For example, single and double sided sheets of copper-on-polyimide are commonly used. Polyimide based films offer good thermal and chemical stability and a low dielectric constant, while copper having high tensile strength, ductility, and flexure has been advantageously used in both flexible circuit and chip scale packaging applications. However, such tapes are relatively expensive, particularly as compared to lead frames and laminate substrates.
Microelectronic packages can be formed by wafer level packaging processes where semiconductor components are packaged while the semiconductor die remain connected in a wafer form. The wafer is subjected to a number of process steps to form package structure and the wafer is diced to free the individual die. Wafer level processing may provide a cost savings advantage. Furthermore, the package footprint can be identical to the die size, resulting in very efficient utilization of area on a circuit panel, e.g., printed wiring board to which the die will eventually be attached. As a result of these features, die packaged in this manner are commonly referred to as wafer level chip scale packages (WLCSP).
In order to save space certain conventional designs have stacked multiple microelectronic chips within a package. This allows the package to occupy a surface area on a substrate that is less than the total surface area of the chips in the stack. However, conventional stacked packages can have disadvantages relating to complexity, cost, thickness and testability.
Amidst this background, there remains a need for improved wafer-scale packaging processes and especially stacked packages.